Currently, CDR circuits are based on timing signals provided by Delay Locked Loops (DLL) or Voltage Controlled Delay Loops (VCDL). An example of such prior art CDR circuits are described in U.S. Pat. No. 5,684,421 issued Nov. 4, 1997 to Chapman et al., which patent is hereby incorporated by reference. In a CDR system an internal clock, derived from a reference Phase-Lock Loop (PLL) clock, is used to oversample incoming data. Based on the results of this oversampled data, a recovered clock is derived by delaying the internal clock so that it provides data sampling adjusted to the center of the “eye” pattern of the received data. FIG. 1 illustrates an example of sampling of a received digital data signal 10 wherein S0 and S1 depict sampling times corresponding to the center of the eye pattern. As also illustrated, sampling at transition points T0 and T1 would not properly detect the received data, although these points are used for data phase detection.
FIG. 2 is a block diagram of a conventional CDR system in which a VCDL component 220 is used to generate multiphase clock signals for a data sampler 230 for sampling serial data 240. In such a VCDL component, the phases of this multiphase clock need to be constantly adjusted to the phase deviations of the incoming data. As proper sampling of the serial data occurs, a Recovered Bit Clock 260 is derived which corresponds in timing (phase and frequency) to the serial data signal. This Recovered Bit Clock 260 is supplied to a filter (e.g., a second order PI filter, as is well-known) which produces a Phase Control Signal 250 which is supplied back to the VCDL component 220. This Phase Control Signal 250 comprises feedback information on adjusting the phase of the multiphase clocks. For example, this signal may comprise instructions that the phase needs to be increased by a fixed amount, decreased by a fixed amount, or left unchanged.
A problem exists in the prior art in that this Phase Control Signal 250 is in the recovered clock domain while the VCDL component operates in the PLL clock domain. That is, the Phase Control Signal 250 is derived and consequently changes as a function of the recovered clock timing. This recovered clock is independent and potentially changing its relation in time to the PLL clock. For the VCDL circuitry to properly utilize the information in this Phase Control Signal, synchronization of this signal relative to the PLL clock needs to be performed.